"Every Ryzen 4000 APU processor that sells now means one less graphics card is needed,"

 I've tried explaining this to people but I am not knowledgeable enough to explain the intricacies appropriately, or plain stupid questions for that matter.

 Is there a simple breakdown somewhere that you know of?

https://wccftech.com/intel-claims-gaming-real-world-benchmarks-leak-10th-gen-cpu
s-vs-amd-ryzen-4000-renoir-apus/

 Obviously Intel has this handled right?

 My favorite part:

"Intel is still relying on benchmarks to showcase the potential of its 10th Gen CPUs whereas its CEO stated that the industry should stop focusing on benchmarks."

https://liliputing.com/2020/08/mozilla-lays-off-250-employees-a-quarter-of-it...



The corporation responsible for developing the Firefox web browser is laying off about a fourth of its workforce. As of 2018, the Mozilla Corporation had over 1,000 full-time employees. Now Mozilla has announced it’s restructuring the organization and laying off 250 people.

Mozilla says the global COVID-19 pandemic has taken a toll on the corporation’s financial resources and downsizing the organization will help ensure it can continue operations.

Among other things, that means closing down Mozilla’s operations in Taipei, Taiwan and in addition to the 250 jobs that are being eliminated, about 60 people will transition to new teams.

Somewhat optimistically, the announcement also suggests Mozilla will try to do more with less by “acting more quickly and nimbly,” and being more open to experimentation, adjustments, and partnerships with outside organizations.

https://videocardz.com/newz/intel-tiger-lake-features-10nm-superfin-architecture

https://liliputing.com/2020/08/intel-tiger-lake-laptops-are-coming-soon-if-th...




OK, we know Intel has just leaked 20 gigs of "top secret" stuff from the abandoned 10nm and 7nm processes that Bob Swan has just recently given up on,
with Bob planning on buying a bunch of TSMC 6nm lithography built production instead.

Some of this older style Intel homemade stuff will still come to market this year anyway (even if it performs significantly no better than some of the faster existing Intel 14nm PC chipsets) mainly because the 10nm process lines are already built now and the lines are up & running as best they can run (and in a bean picker's world such huge capital investments of that size must be run at full rate 24/7 in order to attempt to pay for themselves).

Bob Swan has also said that all the folks he fired a few weeks ago "tended to overcomplicate things".    Wow, what an understatement that was, Bob.

I also understand more of why Bob Swan thinks that all these layers of these esoteric people simply lost track of "competitiveness" and spent all their time designing very very complex technically nice things that could not be brought into reality in a timely fashion on real world Intel equipment and this was why Intel has lost its way.

I think Raja Koduri and Bob Swan holds the final responsibility for allowing this current EXTREMELY EXPENSIVE Tiger Lake "ongoing design error" cluster fook to go to build and Bob Swan needs to be let go as well right after he fires Raj Koduri for this sad non-competitive Tiger Lake mess that will launch on the second of next month.

Intel Tiger Lake (available in units this fall) will swing only 1/2 the CPU core count of the recently released AMD Ryzen 4000 competition but Intel Tiger Lake will actually pull more power from the battery in order to run itself.  

The on board graphics of the two will be somewhat roughly comparable between the two brands (within a 40% advantage going to AMD) but with all the recent Intel cheating and black bag benchmark games that are going on right now in the industry trying to make a real comparison without using near identical laptops is nearly impossible to do.  

Really, until HP or Lenovo come out with the two chips running in the same exact laptop (battery screen and memory the same as close as can be done) a simple empirical test series on the two APUs will not be able to be done.

         ................  Recommendation:  AVOID Intel 10nm and 7nm laptop chipsets like the plague as the sheer expense involved in making this 10nm + and ++  and +++ stuff will be astronomical compared to the already slightly superior and already much less costly AMD Ryzen 4000 processors

https://www.tomshardware.com/news/intel-alder-lake-x86-hybrid-cpu-for-desktops

Intel is trying to make a case internally for Big-bigger for desktop chipsets.  

Just read it, it does not take long.

When you read this, be thinking about TSMC's 6nm lithography two years from now and all the neat Big-little tricks the cell phone boys will be doing with ARM PC chip designs.

I find it refreshing that AMD has taken out actual patents on Big-little for PCs that have johnny come lately Intel having to call theirs Big-bigger.  

It makes me smile some to see Chipzilla on their back foot to the phone boys for a change.


===================================================


And this brings up my final question for the day ---- what is the compute industry going to do about Intel intentionally crippling Intel's competition using Intel's control of the industry BIOS library system (and the base system drivers, let's not forget them).

We are not talking about Intel fixing things so it is working better for Intel's own products (it can't, it is stuck at 14nm and at a poorly working 10nm).
Intel simply can't get any better than AMD.   Intel has tried and tried and tried to get better --- and failed again and again and again.

We are now talking about something different (and far worse).  We are now talking about Intel intentionally screwing up the competitor's functionality REPEATEDLY week after week first with one processor library area followed next week by another BIOS settings area followed next week by a driver area.



It must be sad that the only way you can try to win the race is to secretly trip up the other runners --- repeatedly no less.

I am not the only one who reads the tea leaves this way ......

https://ownsnap.com/amd-zen-4-ryzen-5000-desktop-cpus-might-use-l4-cache-4-th...



Remember last year’s industrial leaks about AMD is up to something with it’s CPUs thread count? Exactly, SMT4 (Simultaneous Multi-Threading) feature may not come to Zen3 but it will be implemented for Zen 4 CPUs running on 5nm transistor shrink with matured strong architecture. It translates into 4 Threads Per Single Core feature that elevates overall performance up to 20-30% apart from the 40-60% bump the processors will be giving to processing power.

Large IPC (Instructions Per Cycle) increase is also seen on horizon by 10-15% uplift in performance since memory bottlenecks can finally be reduced significantly using DDR5 fast access memory. Per SK Hynix claims, the DDR5 memory generation might run at 8400 Mhz effective speed which is a sweet dream of APU users. New AVX-512 instruction set is to be included for sure as previous leaks suggested.

Novel chipset design optimized for Zen 4 futuristic architecture is inbound to Ryzen 5000 processors’ performance tweaking. More importantly, X3D chip packaging solution will be implemented too because AMD strongly presented 3D stacked method to solve many previous unsolved latency issues at it’s Financial Analyst Day two months ago. Obviously, 3D packaging allows billions of transistors getting together stacked in three dimensional positions to achieve maximum efficiency and performance.

Larger Level 2 cache with a size of 1 MB instead of 512 KB per core is also supported by the latest leaks on Zen 4. Possibly, Level 4 cache appears to be featured in some Ryzen 5000 desktop CPU models but not all of the mobile processors. Current PC industry still utilizes Level 3 Caching method so having DDR5 super fast memory in future generation CPUs you might want to think that L4 cache is a necessary complement each other.

Bigger cache sizes will be required to support 4 active threads per processor.   Expect sizable Level 4 caches to be included on models specifically structured to support the heavy use of 4 active threads per processor for large data crunching tasks.

Expect many layered processors at 5nm to support all of this L-1 through L-4 cache stuff.  

Also expect some AMD mobile APU laptops that can do jobs that used to require a Xenon Scalable workstation ......


.......  change, she comes ........

https://www.fool.com/investing/2020/06/15/will-intel-new-chips-widen-moat-vs-...

Intel gestures towards the mobile market again with new chips for lightweight laptops and foldable devices.

Smaller, faster, and more power-efficient
Intel claims the Hybrid chips will fully support Windows 10 applications with a 56% smaller package area, 47% smaller board size, and a 91% reduction in standby power consumption than its comparable Y-series processors.

In terms of real-world applications, Intel expects the chips to offer up to 24% better power efficiency during web browsing, up to 1.7 times better graphics performance, and up to 54% faster conversions of video formats. They could also offer double the throughput for AI-enhanced workloads.

Intel is aiming these CPUs at lightweight laptops and foldable devices. Samsung's Galaxy Book S, Lenovo's ThinkPad X1 Fold, and Microsoft's dual-screen Surface Neo are the first three devices to use the new CPUs.


Once again --- comparing Intel against Intel is both pointless and meaningless.   Intel must do better than QUALCOMM in this market slice, not Intel.      Intel must do better than AMD in this market slice, not Intel.  Intel must do better than ARM Holdings X-series in this market slice, not Intel.

Right now Intel has just now realized they have something to lose while they were deep in the throes of actually losing it .....

And I find it fairly funny that Intel is also "busy losing it" to Intel's business partner Mediatek, the same company Intel buys its radio tower modems from.

And from Samsung, let's not forget good Intel business buddy Samsung, the one Intel has to build all of Intel's most modern chipset trial lots since Intel's own 10nm and 7nm is still acting fairly broken right now.


Seriously, this market slice combat is really all about CHROMEBOOKS ...... with perhaps a side dash of Qualcomm Windows on ARM laptops.

Chromebooks own the education market and are making inroads into business uses .......

Intel does not want to lose Chromebooks, and next year's light duty APUs from AMD may well steal that market segment away from Intel.


====================================================


Nice gesture, Intel.   Now let's think about that astronomical price tag you are putting on your first Foveros stacked Big bigger samples that you are sending out right now .......  

Intel, you may want to rethink that a little bit.   Intel, you are defining the pricing of a market segment right now (intending for you to be the one to fill it) that is actually a "made to order" perfect fit for next year's lower cost higher performance Cezanne AMD 5nm APU's.

Intel is having to compete on PERFORMANCE (Tiger Lake)

Intel is having to compete on BATTERY LIFE (Alder Lake)

With Intel, you can have one or the other ........  NOT BOTH AT THE SAME TIME

With AMD 5nm APUs you get both, and you get a lower price tag and a lower unit cost and much better built in graphics.



When businesses make the wager on which company to use for processors when they plan a new product, they look for what is coming for the next 2 years.

With Intel, you get a vague promise and a 50-50 chance of actually seeing it anywhere close to on time.

AMD, 100% chance of seeing it on time, 25% chance of seeing it up to three months early.

AMD contracts 2 years in advance for TSMC production slots, coming right in behind Apple in the order of build presidence for new lithography waves.    

AMD tends to hit their build slots on the nose with no issues building their products.



Intel wants to go with fully mature "maximum utilization" TSMC process waves, so Intel is coming in 2-3 years past the totally new wave front that Apple rides.

AMD comes in between Apple and Intel time-wise and AMD costs less than either of them by far.